TMP320C203 Datasheet, PDF (47/84 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C203, TMS320C209, TMS320LC203
DIGITAL SIGNAL PROCESSORS
SPRS025B – JUNE 1995 – REVISED AUGUST 1998
timing at V_DD = 5 V with the PLL circuit disabled, divide-by-two mode for TMS320C203^†
PARAMETER
fx
Input clock frequency
TEST CONDITIONS
TA = – 40°C to 85°C, 5 V
MIN MAX
80
0† 57.14
40.96
UNIT
MHz
† _{This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz, but is tested at fx = 6.7 MHz to meet device test time requirements.
switching characteristics over recommended operating conditions for TMS320C203
(see Figure 8)
PARAMETER
’320C203-40
MIN TYP MAX
’320C203-57
MIN TYP MAX
’320C203-80
UNIT
MIN TYP MAX
tc(CO)
Cycle time, CLKOUT1
48.8 2tc(CI)
‡
35 2tc(CI)
‡
25 2tc(CI)
‡ _ns
td(CIH-CO)
Delay time, CLKIN high to
CLKOUT1 high/low
1
11
20
1
11
20
1
9
18 ns
tf(CO)
tr(CO)
Fall time, CLKOUT1
Rise time, CLKOUT1
5§
5
4
ns
5§
5
4
ns
tw(COL)
Pulse duration, CLKOUT1 low
H–3
H H+1 H–3
H H+1 H–3
H H + 1 ns
tw(COH)
Pulse duration, CLKOUT1 high
H–1
H H+3 H–1
H H+3 H–1
H H + 3 ns
‡ _{This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz, but is tested at tc(CI) = 300 ns to meet device test time requirements.
§ _{Values derived from characterization data and not tested}
timing requirements over recommended operating conditions for TMS320C203 (see Figure 8)
’320C203-40 ’320C203-57 ’320C203-80
UNIT
MIN MAX MIN MAX MIN MAX
tc(CI)
Cycle time, CLKIN
25
¶ _17.5
¶ _12.5
¶ _ns
tf(CI)
Fall time, CLKIN§
5
5
4 ns
tr(CI)
Rise time, CLKIN§
5
5
4 ns
tw(CIL) Pulse duration, CLKIN low
11
¶
8
¶
5
¶ _ns
tw(CIH) Pulse duration, CLKIN high
11
¶
8
¶
5
¶ _ns
§ _{Values derived from characterization data and not tested}
¶ _{This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz, but is tested at a minimum tc(CI) = 150 ns to meet device test time requirements.
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