LMK03318 Datasheet, PDF (47/136 Pages) Texas Instruments – Ultra-Low-Noise Jitter Clock Generator Family

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LMK03318
SNAS669A – SEPTEMBER 2015 – REVISED DECEMBER 2015
A logic-high interrupt output (INTR) can also be selected on either status pins to indicate interrupt status from
any of the device vitals listed in R16. In order to use this feature, R17.0 should be set to 1, R14[4:2] must be set
to 111, and R14.0 must be set to 1. The interrupts listed in R16 can be combined in an AND or OR functionality
by programming R17.1. If interrupts stemming from particular device vitals are to be ignored, the appropriate bits
in R14 should be programmed as needed. The contents of R16 can be read back at any time irrespective of
whether the INTR function is chosen in either status pins as long as R17.0 = 1 and the contents of R16 are self-
cleared once the readback is complete. There also exists a “real-time” interrupt register, R13, which indicate
interrupt status from the device vitals irrespective of the state of R17.0. The contents of R13 can be also read
back at any time and are self-cleared once the readback is complete.
10.4.18.1 Loss of Reference
The primary and secondary references can be monitored for their input signal quality and appropriate register
bits and status outputs, if enabled, are flagged if a loss of signal event is encountered. For differential inputs, a
“loss of signal” event occurs when the differential input swing is lower than the threshold as programmed in
R25[3-2] for secondary reference and in R25[1-0] for primary reference. For LVCMOS inputs, a loss of signal
event can be triggered based on either a minimum threshold, programmed in R25[3-2] for secondary reference
and in R25[1-0] for primary reference, or a minimum slew rate of 0.3 V/ns, rising edge or falling edge or both
being monitored based on selections programmed in R25[7-6] for secondary reference and in R25[5-4] for
primary reference.
10.4.18.2 Loss of Lock
The PLL’s loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle
slip. The PLL unlock is detected when a certain number of cycle slips have been exceeded, at which point the
counter is reset. If the loss of lock is intended to toggle a system reset, an RC filter on the status output, which is
programmed to indicate loss of lock, is recommended to avoid rare cycle slips from triggering an entire system
reset.
Table 8. Device Vitals Selection Matrix for STATUS[1:0]
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIGNAL
PRIREF Loss of Signal (LOS)
SECREF Loss of Signal (LOS)
PLL Loss of Lock (LOL)
PLL R Divider, divided by 2 (when R Divider is not bypassed)
PLL N Divider, divided by 2
RESERVED
RESERVED
RESERVED
PLL VCO Calibration Active (CAL)
RESERVED
Interrupt (INTR)
PLL M Divider, divided by 2 (when M Divider is not bypassed)
RESERVED
EEPROM Active
PLL Secondary to Primary Switch in Automatic Mode
RESERVED
When the status pins are programmed as 3.3-V LVCMOS PLL clock outputs with fast output rise/fall time setting,
they support up to 200 MHz operation and each output can independently be programmed to different
frequencies. Each output has the option to be muted or not, in case the PLL from which it is derived loses lock,
by programming R23 and when muted, the output is held at a static state depending on the programmed output
type/polarity. in a loss-of-lock event. In order to reduce coupling onto the high-speed outputs, the output rise/fall
time can be modified in R49 to support slower slew rates.
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