DP83846A_11 Datasheet, PDF (47/62 Pages) Texas Instruments – DsPHYTER - Single 10/100 Ethernet Transceiver

6.1 Reset Timing
V_CC
X1 Clock
T1.0.4
T1.0.1
HARDWARE
RSTN
MDC
te ^{Latch-In of Hardware}
Configuration Pins
Dual Function Pins
le ^{Become Enabled As Outputs}
32 CLOCKS
T1.0.2
T1.0.3
INPUT
OUTPUT
Parameter
Description
Notes
Min Typ Max
o _T1.0.1
Post RESET Stabilization time MDIO is pulled high for 32-bit se-
3
prior to MDC preamble for regis- rial management initialization
ter accesses
s _T1.0.2
Hardware Configuration Latch-in Hardware Configuration Pins are
3
Time from the Deassertion of RE- described in the Pin Description
SET (either soft or hard)
section
T1.0.3
Hardware Configuration pins
3.5
b transition to output drivers
T1.0.4
RESET pulse width
X1 Clock must be stable for a
160
minimum of 160us during RESET
pulse low time.
Units
µs
µs
µs
µs
O ^{Note1: Software Reset should be initiated no sooner then 500 µs after power-up or the deassertion of hardware reset.}
Note2: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
46
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