ADC3441 Datasheet, PDF (47/83 Pages) Texas Instruments – Analog-to-Digital Converter

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ADC3441, ADC3442, ADC3443, ADC3444
SBAS670A – JULY 2014 – REVISED OCTOBER 2015
Clock Buffer
LPKG
2 nH
20 Ÿ
CLKP
CBOND
1 pF
5 kŸ
CEQ
CEQ
RESR
100 Ÿ
0.95 V
CLKM
LPKG
2 nH
CBOND
1 pF
CEQ
5 kŸ
20 Ÿ
RESR
100 Ÿ
NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 139. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 140. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
CMOS
Clock Input
0.1 mF
CLKP
0.1 mF
CLKM
Device
Figure 140. Single-Ended Clock Driving Circuit
9.3.2.1 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization
noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter
sets SNR for higher input frequencies.
SNR_ADC[dBc]
20 ˜log
SNR
2
§ · Quantizatoin Noise
¨¨¹⁰ ¸¸ ²⁰
©
¹
SNR
2
§ · Thermal Noise
¨¨©¹⁰ ¸¸¹ ²⁰
¨¨©§¹⁰
SNR
Jitter
20
¸·²
¸¹
(1)
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.
SNR_Jitter[dBc] 20 ˜ log( 2S ˜ f_in ˜T_Jitter )
(2)
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