ADC08D1000QML Datasheet, PDF (47/50 Pages) National Semiconductor (TI) – High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

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ADC08D1000QML, ADC08D1000QML-SP
ADC08D1000WG-QV
SNAS352G – JANUARY 2007 – REVISED MARCH 2013
Since digital switching transients are composed largely of high frequency components, the skin effect tells us that
total ground plane copper weight will have little effect upon the logic-generated noise. Total surface area is more
important than is total ground plane volume. Coupling between the typically noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or near any linear component or power supply trace or
plane that services analog or mixed signal components as the resulting common return current path could cause
fluctuation in the analog input “ground” return of the ADC, causing excessive noise in the conversion result.
Generally, we assume that analog and digital lines should cross each other at 90° to avoid getting digital noise
into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The
input clock lines should be isolated from ALL other lines, analog AND digital. The generally accepted 90°
crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance
at high frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
This is especially important with the low level drive required of the ADC08D1000. Any external component (e.g.,
a filter capacitor) connected between the converter's input and ground should be connected to a very clean point
in the analog ground plane. All analog circuitry (input amplifiers, filters, etc.) should be separated from any digital
components.
DYNAMIC PERFORMANCE
The ADC08D1000 is a.c. tested and its dynamic performance is ensured. To meet the published specifications
and avoid jitter-induced noise, the clock source driving the CLK input must exhibit low rms jitter. The allowable
jitter is a function of the input frequency and the input signal level, as described in THE CLOCK INPUTS.
It is good practice to keep the ADC input clock line as short as possible, to keep it well away from any other
signals and to treat it as a transmission line. Other signals can introduce jitter into the input clock signal. The
clock signal can also introduce noise into the analog path if not isolated from that path.
Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection
to ground. This is because this path from the die to ground is a lower impedance than offered by the package
pins.
USING THE SERIAL INTERFACE
The ADC08D1000 may be operated in the non-extended control (non-Serial Interface) mode or in the extended
control mode. Table 12 and Table 13 describe the functions of pins 3, 4, 14 and 127 in the non-extended control
mode and the extended control mode, respectively.
Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial Interface is not active and all controllable functions
are controlled with various pin settings. That is, the full-scale range and input coupling (a.c. or d.c.) are controlled
with pin settings. The non-extended control mode is used by setting pin 14 high or low, as opposed to letting it
float. Table 12 indicates the pin functions of the ADC08D1000 in the non-extended control mode.
Table 12. Non-Extended Control Mode Operation (Pin 14 High or Low)
Pin
Low
High
Floating
3
0.50 V_P-P Output
0.70 V_P-P Output
n/a
4
OutEdge = Neg
OutEdge = Pos
DDR
127
CalDly Low
CalDly High
DES
14
650 mV_P-P input range
870 mV_P-P input range
Extended Control Mode
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