LM3S1138 Datasheet, PDF (468/638 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
13.2
Signal Description
Table 13-1 on page 468 and Table 13-2 on page 468 list the external signals of the SSI module and
describe the function of each. The SSI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and
SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 302) should be set to choose the SSI function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 279.
Table 13-1. SSI Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSI0Clk
28
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
I/O
TTL
SSI module 0 frame signal.
SSI0Rx
30
I
TTL
SSI module 0 receive.
SSI0Tx
31
O
TTL
SSI module 0 transmit.
SSI1Clk
72
I/O
TTL
SSI module 1 clock.
SSI1Fss
73
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
74
I
TTL
SSI module 1 receive.
SSI1Tx
75
O
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 13-2. SSI Signals (108BGA)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSI0Clk
M4
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
I/O
TTL
SSI module 0 frame signal.
SSI0Rx
L5
I
TTL
SSI module 0 receive.
SSI0Tx
M5
O
TTL
SSI module 0 transmit.
SSI1Clk
A11
I/O
TTL
SSI module 1 clock.
SSI1Fss
B12
I/O
TTL
SSI module 1 frame signal.
SSI1Rx
B11
I
TTL
SSI module 1 receive.
SSI1Tx
A12
O
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
13.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
468
July 15, 2014
Texas Instruments-Production Data