LM3S1911 Datasheet, PDF (465/592 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S1911 Microcontroller
13.3
Functional Description
Each I²C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I²C bus configuration is shown in Figure 13-2 on page 465.
See “Inter-Integrated Circuit (I²C) Interface” on page 553 for I²C timing diagrams.
Figure 13-2. I²C Bus Configuration
SCL
SDA
RPUP
RPUP
I2CSCL I2CSDA
Stellaris®
SCL
SDA
3rd Party Device
with I²C Interface
I²C Bus
SCL
SDA
3rd Party Device
with I²C Interface
13.3.1
I²C Bus Functional Overview
The I²C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I²C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 465) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
13.3.1.1
START and STOP Conditions
The protocol of the I²C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
13-3 on page 465.
Figure 13-3. START and STOP Conditions
SDA
SCL
START
condition
STOP
condition
SDA
SCL
13.3.1.2
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 13-4 on page 466. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
July 16, 2014
465
Texas Instruments-Production Data