TMS570LS0714_17 Datasheet, PDF (46/163 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS0714
SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016
www.ti.com
6.4 Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
6.4.1 Causes of Warm Reset
Table 6-5. Causes of Warm Reset
DEVICE EVENT
Power-Up Reset
Oscillator fail
PLL slip
Watchdog exception / Debugger reset
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
SYSTEM STATUS FLAG
Exception Status Register, bit 15
Global Status Register, bit 0
Global Status Register, bits 8 and 9
Exception Status Register, bit 13
Exception Status Register, bit 5
Exception Status Register, bit 4
Exception Status Register, bit 3
6.4.2 nRST Timing Requirements
Table 6-6. nRST Timing Requirements⁽¹⁾
t_v(RST)
Valid time, nRST active after nPORRST inactive
Valid time, nRST active (all other System reset
conditions)
MIN
2256t_c(OSC)
32t_c(VCLK)
Filter
time
nRST
pin;
t_f(nRST)
pulses less than MIN will be filtered out, pulses greater
475
than MAX will generate a reset
(1) Specified values do not include rise/fall times. For rise and fall timings, see Table 7-2.
MAX UNIT
ns
2000
ns
46
System Information and Electrical Specifications
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