TLV320AIC3262_14 Datasheet, PDF (46/65 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Stereo Class-D Speaker Amplifier

TLV320AIC3262
SLAS679 – DECEMBER 2011
Table 11. Overview – DAC Predefined Processing Blocks
Processing
Block No.
PRB_P1 ⁽¹⁾
PRB_P2
PRB_P3
PRB_P4
PRB_P5
PRB_P6
PRB_P7
PRB_P8
PRB_P9
PRB_P10
PRB_P11
PRB_P12
PRB_P13
PRB_P14
PRB_P15
PRB_P16
PRB_P17
PRB_P18
PRB_P19
PRB_P20
PRB_P21
PRB_P22
PRB_P23
PRB_P24
PRB_P25
PRB_P26
Interpolation
Filter
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
A
A
A
D
Channel
Stereo
Stereo
Stereo
Left
Left
Left
Stereo
Stereo
Stereo
Stereo
Stereo
Left
Left
Left
Left
Left
Stereo
Stereo
Stereo
Left
Left
Left
Stereo
Stereo
Stereo
Stereo
1st Order
IIR Available
No
Yes
Yes
No
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Num. of
DRC
3D
Biquads
3
No
No
6
Yes
No
6
No
No
3
No
No
6
Yes
No
6
No
No
0
No
No
4
Yes
No
4
No
No
6
Yes
No
6
No
No
0
No
No
4
Yes
No
4
No
No
6
Yes
No
6
No
No
0
No
No
4
Yes
No
4
No
No
0
No
No
4
Yes
No
4
No
No
2
No
Yes
5
Yes
Yes
5
Yes
Yes
0
No
No
(1) Default
For more detailed information see the Application Reference Guide, SLAU309.
www.ti.com
Beep
Generator
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
RC Class
8
12
10
4
6
5
5
9
7
9
7
3
4
4
5
4
3
6
4
2
3
2
8
12
13
1
Powertune
The TLV320AIC3262 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application. The TLV320AIC3262 PowerTune
modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback
(DAC) path.
For more detailed information see the Application Reference Guide, SLAU309.
Clock Generation and PLL
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3262.
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