DLPC350_14 Datasheet, PDF (46/62 Pages) Texas Instruments – Digital Controller for Portable Advanced Light Control

DLPC350
DLPS029C – APRIL 2013 – REVISED MARCH 2014
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11 Layout
11.1 Layout Guidelines
11.1.1 DMD Interface Design Considerations
The DMD interface is modeled after the low-power DDR memory (LPDDR) interface. In order to minimize power
dissipation, the LPDDR interface is defined to be unterminated. As a result, PCB signal integrity management is
imperative. Impedance control and crosstalk mitigation is critical to robust operation. LPDDR board design
recommendations include trace spacing that is three times the trace width, impedance control within 10%, and
signal routing directly over a neighboring reference plane (ground or 1.9-V plane).
DMD Interface performance is also a function of trace length, so the length of the line will limit performance. The
DLPC350 controller will only work over a narrow range of DMD signal routing lengths at 120 MHz. Ensuring
positive timing margins requires attention to many factors.
As an example, the DMD interface system timing margin can be calculated as follows.
Setup Margin = (DLPC350 Output Setup) – (DMD Input Setup) – (PCB Routing Mismatch) – (PCB SI
Degradation)
Hold-Time Margin = (DLPC350 Output Hold) – (DMD Input Hold) – (PCB Routing Mismatch) – (PCB SI
Degradation)
PCB SI degradation corresponds signal integrity degradation due to PCB affects, which includes simultaneously
switching output (SSO) noise, crosstalk, and inter-symbol interface (ISI). Additionally, PCB routing mismatch can
be budgeted via controlled PCB routing.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design
guidelines are provided. They describe an interconnect system that satisfies both waveform quality and timing
requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these
recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab
measurements.
11.1.2 DMD Termination Requirements
Table 15 lists the termination requirements for the DMD interface. These series resistors should be placed as
close to the DLPC350 pins as possible while following all PCB guidelines.
Table 15. Termination Requirements for DMD Interface
SIGNALS
DMD_D(14:0), DMD_TRC, DMD_SCTRL,
DMD_LOADB, DMD_DRC_STRB,
DMD_DRC_BUS, DMD_SAC_CLK, and
DMD_SAC_BUS
DMD_DCLK
DMD_DRC_OE
SYSTEM TERMINATION
External 5-Ω series termination at the transmitter
External 5-Ω series termination
External 0-Ω series termination. This signal must be
externally pulled-up to VDD_DMD via a 30-kΩ to
51-kΩ resistor
46
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