AFE5818 Datasheet, PDF (46/156 Pages) Texas Instruments – 16-Channel, Ultrasound, Analog Front-End

AFE5818
SBAS687B – FEBRUARY 2015 – REVISED AUGUST 2015
www.ti.com
9.3.4.2 System Clock Configuration for Multiple Devices
To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to
generate individual sampling clocks for each channel. For all channels, the clock is matched from the source
point to the sampling circuit of each of the eight internal devices. The variation on this delay is described in the
Aperture Delay parameter of the Output Interface Timing Characteristics table. Variation is described by the
aperture jitter parameter of the Output Interface Timing Characteristics table.
The system clock input can be driven by differential clocks (sine wave, LVPECL, or LVDS) or single-ended
clocks (LVCMOS). In the single-ended case, TI recommends the use of low-jitter square signals (LVCMOS
levels, 1.8-V amplitude). See technical brief, Clocking High-Speed Data Converters, SLYT075 for further details
on the theory.
The jitter cleaners CDCM7005, CDCE72010, or LMK048X series are suitable to generate the system clock and
ensure high performance for the 14-bit device resolution. Figure 74 shows a clock distribution network.
FPGA Clock,
Noisy Clock
n × (5 MHz to 100 MHz)
TI Jitter Cleaner
LMK048X
CDCE72010
CDCM7005
5-MHz to 100-MHz
ADC CLK
CDCLVP1208
LMK0030X
LMK01000
The CDCE72010 has 10
outputs
8 Synchronized
DUT System CLKs
Figure 74. System Clock Distribution Network
46
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