TMS320F2810_14 Datasheet, PDF (45/172 Pages) Texas Instruments – Digital Signal Processors

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
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INT1
INT2
INT11
INT12
IFR[12:1]
(Flag)
IER[12:1]
(Enable)
SPRS174T – APRIL 2001 – REVISED MAY 2012
INTM
MUX
1
0
Global
Enable
CPU
INTx _MUX
PIEACKx
(Enable/Flag)
(Enable)
PIEIERx[8:1]
(Flag)
PIEIFRx[8:1]
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
Figure 3-7. Multiplexing of Interrupts Using the PIE Block
From
Peripherals
or
External
Interrupts
Table 3-12. PIE Peripheral Interrupts⁽¹⁾
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
PIE INTERRUPTS
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
XINT1
Reserved
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT2
Reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
INT3
Reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
INT4
Reserved
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
INT5
Reserved
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
INT6
Reserved Reserved
MXINT
(McBSP)
MRINT
(McBSP)
Reserved
Reserved
SPITXINTA SPIRXINTA
(SPI)
(SPI)
INT7
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT9
Reserved
Reserved
ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
(CAN)
(CAN)
(SCI-B)
(SCI-B)
(SCI-A)
(SCI-A)
INT10
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT11
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT12
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(1) Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
• No peripheral within the group is asserting interrupts.
• No peripheral interrupts are assigned to the group (example PIE group 12).
Copyright © 2001–2012, Texas Instruments Incorporated
Functional Overview
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