LMP90077_16 Datasheet, PDF (45/70 Pages) Texas Instruments – Sensor AFE System: Multi-Channel, Low-Power 16-Bit Sensor AFE

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BIT BIT SYMBOL
[0] SPI_RST
LMP90077, LMP90078, LMP90079, LMP90080
SNAS521H – JULY 2011 – REVISED JANUARY 2016
Table 9. SPI_RESET
SPI RESET CONTROL (ADDRESS 0x02)
BIT DESCRIPTION
SPI Reset Enable
0x0 (default): SPI Reset Disabled
0x1: SPI Reset Enabled⁽¹⁾
BIT BIT SYMBOL
[7:2] Reserved
[1:0] PWRCN
Table 10. PWRCN
POWER MODE CONTROL AND STATUS (ADDRESS 0x08)
BIT DESCRIPTION
-
Power Control
Write Only – power down mode control
0x0: Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
Read Only – the present mode is:
0x0 (default): Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
(1) Once written, the contents of this register are sticky. That is, the content of this register cannot be changed with subsequent write.
However, a Register reset clears the register as well as the sticky status.
9.6.2 ADC Registers
BIT BIT SYMBOL
[7:1] Reserved
0 RESTART
Table 11. ADC_RESTART
ADC RESTART CONVERSION (ADDRESS 0x0B)
BIT DESCRIPTION
-
Restart conversion
1: Restart conversion.
BIT BIT SYMBOL
7 Reserved
6 RESET_SYSCAL
5 CLK_EXT_DET
4 CLK_SEL
Table 12. ADC_AUXCN
ADC AUXILIARY CONTROL (ADDRESS 0x12)
BIT DESCRIPTION
-
The System Calibration registers (CHx_SCAL_OFFSET and CHx_SCAL_GAIN) are:
0 (default): preserved even when "REG_AND_CNV_RST" = 0xC3.
1: reset by setting "REG_AND_CNV_RST" = 0xC3.
External clock detection
0 (default): "External Clock Detection" is operational
1: "External-Clock Detection" is bypassed
Clock select – only valid if CLK_EXT_DET = 1
0 (default): Selects internal clock
1: Selects external clock
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