AFE5803_14 Datasheet, PDF (45/53 Pages) Texas Instruments – Fully Integrated, 8-Channel Ultrasound Analog Front End, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 158 mW/CH

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AFE5803
SLOS763A – JANUARY 2012 – REVISED JANUARY 2012
3.3 V
130 Ω
CDCM7005
CDCE72010
LVPECL
83 Ω
3.3 V 0.1 μF
130 Ω
0.1 μF
AFE
CLOCKs
(a) LVPECL Configuration
CDCE72010
LVDS
100 Ω ^{0.1 μF}
0.1 μF
AFE
CLOCKs
(b) LVDS Configuration
CLOCK
SOURCE
0.1μF
50 Ω
0.1μF
0.1μF
AFE
CLOCKs
0.1μF
(c) Transformer Based Configuration
CMOS CLK
Driver
AFE
CMOS CLK
CMOS
(d) CMOS Configuration
Figure 76. Clock Configurations
S0503-01
Special considerations should be applied in such a clock distribution network design. In typical ultrasound
systems, it is preferred that all clocks are generated from a same clock source, such as CW clocks, audio ADC
clocks, RF ADC clock, pulse repetition frequency signal, frame clock and etc. By doing this, interference due to
clock asynchronization can be minimized.
ADC Reference Circuit
The ADC’s voltage reference can be generated internally or provided externally. When the internal reference
mode is selected, the REFP/M becomes output pins and should be floated. When 3[15] =1 and 1[13]=1, the
device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a
1.4V reference voltage and REFP/M must be left open. Since the input impedance of the VREF_IN is high, no
special drive capability is required for the 1.4V voltage reference
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