TSB81BA3D_12 Datasheet, PDF (44/61 Pages) Texas Instruments – IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
PRINCIPLES OF OPERATION (1394B INTERFACE)
LLC service request (continued)
Table 24. Request Stream Bit Length
REQUEST TYPE
Bus request
Read register request
Write register request
Link notification request
PHY-link interface reset request
NUMBER OF BITS
11
10
18
6
6
Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0
is required at the end of the stream. The second through fifth bits of the request stream indicate the type of the
request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream.
The LREQ terminal is normally low.
Table 25 show the encoding for the request type.
Table 25. Request Type Encoding
LR1−LR4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NAME
Reserved
Immed_Req
Next_Even
Next_Odd
Current
Reserved
Isoch_Req_Even
Isoch_Req_Odd
Cyc_Start_Req
Reserved
Reg_Read
Reg_Write
Isoch_Phase_Even
Isoch_Phase_Odd
Cycle_Start_Due
Reserved
DESCRIPTION
Reserved
Immediate request. Upon detection of idle, the PHY arbitrates for the bus.
Next even request. The PHY arbitrates for the bus to send an asynchronous packet in the even fairness
interval phase.
Next odd request. The PHY arbitrates for the bus to send an asynchronous packet in the odd fairness
interval phase.
Current request. The PHY arbitrates for the bus to send an asynchronous packet in the current fairness
interval.
Reserved
Isochronous even request. The PHY arbitrates for the bus to send an isochronous packet in the even
isochronous period.
Isochronous odd request. The PHY arbitrates for the bus to send an isochronous packet in the odd
isochronous period.
Cycle start request. The PHY arbitrates for the bus to send a cycle start packet.
Reserved
Register read request. The PHY returns the specified register contents through a status transfer.
Register write request. Write to the specified register in the PHY.
Isochronous phase even notification. The link reports to the PHY that:
1) A cycle start packet has been received
2) The link has set the isochronous phase to even.
Isochronous phase odd notification. The link reports to the PHY that:
1) A cycle start packet has been received
2) The link has set the isochronous phase to odd.
Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception.
Reserved
For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 26.
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