TPS65290_16 Datasheet, PDF (44/56 Pages) Texas Instruments – Low-Quiescent-Current, Multi-Mode PMIC

TPS65290
SLVSBY5C – APRIL 2013 – REVISED MARCH 2016
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One method of mitigating these effects is to place a capacitor with low equivalent series resistance (ESR) across
the battery. The battery charges the capacitor between discharge pulses, and the capacitor delivers the pulse
current to the load. Determination of the necessary capacitance requires the following parameters:
• Battery impedance (at temperature and state-of-charge)
• Battery voltage (as a function of state-of-charge)
• Operating temperatures
• Pulse current amplitude
• Pulse current duration
• Allowable voltage drop during pulse discharge
Use the following equations to calculate the output capacitance needed to deliver the specified pulse current of a
known duration and the latency time that required between pulses to allow the battery to recharge the capacitor.
Both formulas assume that the capacitor ESR is sufficiently low to result in negligible internal voltage drop while
delivering the specified pulse current; consequently, only the battery resistance is considered in the formula used
to compute capacitor charging time, and only the load resistance is considered when computing the capacitance
needed to deliver the discharge current.
The first step in creating a battery-capacitor couple for pulse-current applications is to size the capacitance using
the discharge formula in Equation 5.
C = t / R × [–ln (V_MIN / V_MAX)]
where
• C = output capacitance in parallel with battery
• t = pulse duration
• R = load resistance = V_O(average) / Ipulse
(5)
V_MIN and V_MAX are determined by the combination of the battery voltage at a given state-of-charge and the
operating voltage requirement of the external circuit. Once the capacitance has been determined, the capacitor
charging time can be calculated using the charge formula in Equation 6.
t = R × C × [–ln (1 – V_MIN / V_MAX)]
where
• t = capacitor charging time from V_MIN to V_MAX
• R = battery resistance
• C = output capacitance in parallel with battery
(6)
Again, V_MIN and V_MAX are functions of the battery voltage and the circuit operating specifications. Battery
resistance varies according to temperature and state-of-charge as described previously. Worst-case conditions
are often applied to the calculations to ensure proper system operation over temperature extremes, battery
condition, capacitance tolerance, etc.
Due to the high input impedance of the battery used, a high-value input capacitor on the order of thousands of
microfarads is therefore placed at the battery input to store charge. During the RF transmission phase that takes
on the order of 5 ms to10 m, the storage capacitor provides power for transition. The input voltage, V_I, drops
from 3.6 V at the beginning of the operation to about 2 V at the receive time. The main LDO is powered by
VMAX, which would be at the buck-boost output during this transition. The blocks that would see low-voltage
operation of VIN are buck-boost and digital logic. The buck-boost is designed to work down to 1.8 V of typical
falling input voltage. This is for when buck-boost was enabled at a higher input voltage, started up successfully,
and then its input voltage falls. If buck-boost starts from a disabled mode, rising VIN voltage is higher.
Digital reset (nPUC) is designed for a rising VIN voltage of 1.76 V and falling voltage of 1.25 V. To prevent digital
logic from reset, the recovery voltage comparator levels should be set higher than falling voltage (that is, 1.9 V).
If the recovery voltage is lower, or the feature is disabled, PMIC can be reset. When reset happens, PMIC
disables both the main LDO, the BB block (if BB_EN = 0), and all switches. However, VMICRO function will be
still provided. After digital reset and when all blocks are disabled, the input voltage will rise again, and PMIC
starts again with default register values.
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