TMS320C5535 Datasheet, PDF (44/155 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

TMS320C5535
TMS320C5534, TMS320C5533, TMS320C5532
SPRS737 – AUGUST 2011
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Table 3-12. SD0 Terminal Functions
SIGNAL
NAME
SD0_CLK/
I2S0_CLK/
GP[0]
SD0_CMD/
I2S0_FS/
GP[1]
SD0_D3/
GP[5]
SD0_D2/
GP[4]
SD0_D1/
I2S0_RX/
GP[3]
SD0_D0/
I2S0_DX/
GP[2]
NO.
TYPE ⁽¹⁾
(2)
OTHER ^{(3) (4)}
DESCRIPTION
SD
M8 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between SD0, I2S0, and GPIO.
For SD, this is the SD0 data clock output SD0_CLK.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
M10 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between SD0, I2S0, and GPIO.
For SD, this is the SD0 command I/O output SD0_CMD.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
P7 I/O/Z
N13 I/O/Z
P6 I/O/Z
J1 I/O/Z
IPD
DV_DDIO
BH
IPD
DV_DDIO
BH
IPD
DV_DDIO
BH
IPD
DV_DDIO
BH
The SD0_D3 and SD0_D2 pins are multiplexed between SD0 and GPIO.
The SD0_D1 and SD0_D0 pins are multiplexed between SD0, I2S0, and GPIO.
In SD mode, these pins are the SD0 nibble wide bi-directional data bus.
Mux control via the SP0MODE bits in the EBSR.
The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1
register.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD/IPU, if applicable, or externally terminate the pins.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
44
Device Pins
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