ADS5294 Datasheet, PDF (44/67 Pages) Texas Instruments – Octal Channel 14-Bit, 80 MSPS High-SNR and Low-Power ADC

ADS5294
SLAS776B – NOVEMBER 2011 – REVISED JULY 2012
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Where k is set as described by the HPF_corner registers (one for each channel). Also the HPF_EN bit in each
register needs to be set to enable the HPF feature for each channel.
BIT CLOCK PROGRAMMABILITY
ADDR.
(HEX)
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
42
XX
PHASE_DDR<1:0>
46
1
X
EN_SDR
46
1
X
FALL_SDR
The output interface of the ADS5294 is normally a DDR interface, with the LCLK rising edge and falling edge
transitions in the middle of alternate data windows. This default phase is shown in Figure 51.
PHASE_DDR<1:0> = 10
ADCLKp
LCLKp
OUTp
Figure 51. Default Phase of LCLK
The phase of LCLK can be programmed relative to the output frame clock and data using bits
PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 52.
PHASE_DDR<1:0> = 00
PHASE_DDR<1:0> = 10
ADCLKp
ADCLKp
LCLKp
OUTp
LCLKp
OUTp
PHASE_DDR<1:0> = 01
ADCLKp
ADCLKp
PHASE_DDR<1:0> = 11
LCLKp
LCLKp
OUTp
OUTp
Figure 52. Phase Programmability Modes for LCLK
44
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