TM4C123AH6PM_15 Datasheet, PDF (437/1238 Pages) Texas Instruments – Tiva TM4C123AH6PM Microcontroller

Tiva^™ TM4C123AH6PM Microcontroller
Register 124: Run Mode Clock Gating Control Register 1 (RCGC1), offset
0x104
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before
any registers in that module are accessed.
Important: This register is provided for legacy software support only.
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCTIMER)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as Timer 0), the write causes proper operation, but the value of that
bit is not reflected in this register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
COMP1 COMP0
Type RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
15
reserved
Type RO
Reset
0
14
I2C1
RO
0
13
reserved
RO
0
12
I2C0
RO
0
11
10
reserved
RO
RO
0
0
9
QEI1
RO
0
8
QEI0
RO
0
23
22
21
reserved
RO
RO
RO
0
0
0
7
6
reserved
RO
RO
0
0
5
SSI1
RO
0
20
19
18
17
16
TIMER3 TIMER2 TIMER1 TIMER0
RO
RO
RO
RO
RO
0
0
0
0
0
4
SSI0
RO
0
3
2
1
0
reserved UART2 UART1 UART0
RO
RO
RO
RO
0
0
0
0
Bit/Field
31:26
Name
reserved
Type
RO
Reset
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
437
Texas Instruments-Production Data