TMS470R1VF334A Datasheet, PDF (43/54 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

TMS470R1VF334
16/32-BIT RISC FLASH MICROCONTROLLER
SCIn isosynchronous mode timings — external clock
SPNS081D – MARCH 2003 – REVISED AUGUST 2006
timing requirements for external clock SCIn isosynchronous mode^†‡ (see Figure 16)
NO.
1 t_c(SCC)
2 t_w(SCCH)
3 t_w(SCCL)
4 t_d(SCCH-TXV)
5 t_v(TX)
6 t_su(RX-SCCL)
7 t_v(SCCL-RX)
Cycle time, SCInCLK^§
Pulse duration, SCInCLK high
Pulse duration, SCInCLK low
Delay time, SCInCLK high to SCInTX valid
Valid time, SCInTX data after SCInCLK low
Setup time, SCInRX before SCInCLK low
Valid time, SCInRX data after SCInCLK low
MIN
8t_c(ICLK)
0.5t_c(SCC) – 0.25t_c(ICLK)
0.5t_c(SCC) – 0.25t_c(ICLK)
2t_c(SCC)–10
0
2t_c(ICLK) + 10
MAX
0.5t_c(SCC) + 0.25t_c(ICLK)
0.5t_c(SCC) + 0.25t_c(ICLK)
2t_c(ICLK) + 12 + t_r
† t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
‡ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
§ When driving an external SCInCLK, the following must be true: t_c(SCC) ≥ 8t_c(ICLK)
UNIT
ns
ns
ns
ns
ns
ns
ns
SCICLK
SCITX
SCIRX
1
3
4
2
5
Data Valid
6
7
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
43