USBN9604-28MX Datasheet, PDF (42/62 Pages) Texas Instruments – USBN9603 USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support

7.0 Register Set (Continued)
7.2.9 Mirror Register (MIR)
This is a read only register. Since reading it does not alter the state of the TXSx or RXSx register to which it points, the
firmware can freely check the status of the channel.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
STAT
-
r
STAT
Status. This field mirrors the status bits of the transmitter or receiver selected by the DSRC2-0 field in the DMACNTRL reg-
ister (DMA need not be active or enabled). It corresponds to TXSx or RXSx, respectively.
7.2.10 DMA Count Register (DMACNT)
This register allows a maximum count to be specified for ADMA operations
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DCOUNT7-0
-
r/w
DCOUNT
DMA Count. This field is decremented on completion of a DMA operation until it reaches 0. Then the DCNT bit in the DMA
Event register is set, only when the next successful DMA operation is completed. This register does not underflow.
For receive operations, this count decrements when the packet is received successfully, and then transferred to memory via
DMA.
For transmit operations, this count decrements when the packet is transferred from memory via DMA, and then transmitted
successfully.
DCOUNT should be set as follows: DCOUNT = (No. of packets to transfer) - 1
If a DMACNT write operation occurs simultaneously with the decrement operation, the write takes precedence.
7.2.11 DMA Error Register (DMAERR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
AEH
DMAERRCNT
0
0
0
0
0
0
0
r/w
r/w
DMAERRCNT
DMA Error Counter. In conjunction with the automatic error handling feature, this counter defines the maximum number of
consecutive bus errors before ADMA mode is stopped. Firmware can set the 7-bit counter to a preset value. Once ADMA is
started, the counter decrements from the preset value by 1 every time a bus error is detected. Every successful transaction
resets the counter back to the preset value. When ADMA mode is stopped, the counter is also set back to the preset value.
If the counter reaches 0 and another erroneous packet is detected, the DERR bit in the DMA Event register is set. For more
information on the effect of setting DERR, see Section 7.2.7. This register cannot underrun.
DMAERRCNT should be set as follows: DMAERRCNT = 3D (Max. no. of allowable transfer attempts) - 1
A write access to this register is only possible when ADMA is inactive. Otherwise, it is ignored. Reading from this register
while ADMA is active returns the current counter value. Reading from it while ADMA is inactive returns the preset value. The
counter decrements only if AEH is set (automatic error handling activated).
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