TPS43331-Q1 Datasheet, PDF (42/50 Pages) Texas Instruments – DUAL SWITCHER AND LINEAR REGULATORS

TPS43331-Q1
SLVSA38 – DECEMBER 2009
www.ti.com
Power Dissipation Derating
The power dissipation curve (see Figure 40) is based on attachment of the exposed power pad to the printed
circuit board with multi layer FR4. The data is based of JEDEC JESD 51-5 standard board with thermal vias and
high K profile. The user must review Texas Instruments TI Technical Brief (SLMA002) for recommended method
of exposed pad attachment.
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
140
160
Temperature (C)
Figure 40. Power Dissipation Derating
Grounding and Circuit Layout Considerations
The TPS43331 has two separate ground terminations (AGND and PGND) pins. The ground signal consists of a
plane to minimize its impedance. Try to separate the low signal ground termination from the power ground signal.
The high power noisy circuits like the output, synchronous rectifier, MOSFET driver decoupling capacitor and the
input capacitor should be connected to the PGND plane. The AGND plane should only make a single point
connection to the PGND plane.
The sensitive nodes like the feedback resistor divider, oscillator resistor (to set frequency), current sense, and
compensation circuitry should be connected to the AGND plane.
Try and minimize the high current carrying loops to a minimum, by ensuring optimal component placement.
Ensure the bypass capacitors are located as close as possible to their respective power and ground pins.
Sensitive circuits such as sense feedback , frequency setting resistor for the oscillator, current sense and
compensation circuits should NOT be located near the dv/dt nodes, these include the gate drive outputs, phase
pins and boost circuits (bootstrap).
42
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