TAS3108DCPR Datasheet, PDF (42/63 Pages) Texas Instruments – AUDIO DIGITAL SIGNAL PROCESSORS

Not Recommended for New Designs
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
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7.3 I²C Memory Load Control and Data Registers (0x04 and 0x05)
Registers 0x04 (Table 7-3) and 0x05 (Table 7-4) allow the user to download TAS3108/TAS3108IA
program code and data directly from the system I²C controller. This mode is called the I²C slave mode
(from the TAS3108/TAS3108IA point-of-view). See the TAS3108/TAS3108IA Firmware Programmer's
Guide (SLEU067) for more details.
BYTE
1–2
3–4
5
6–7
7–8
Table 7-3. TAS3108/TAS3108IA Memory Load Control Register (0x04)
DATA BLOCK FORMAT
Checksum code
Memory to be loaded
Unused
Starting TAS3108/TAS3108IA memory
address
Number of data bytes to be transferred
SIZE
2 bytes
2 bytes
1 byte
2 bytes
NOTES
Checksum of bytes 2 through N + 8. If this is a termination header,
this value is 0000.
0 Microprocessor program memory
1 Microprocessor external data memory
2 Audio DSP core program memory
3 Audio DSP core coefficient memory
4 Audio DSP core data memory
5–15 Reserved for future expansion
Reserved for future expansion
If this is a termination header – this value is 0000.
2 bytes If this is a termination header – this value is 0000.
BYTE
1
2
3
4
5
6
7
8
Table 7-4. TAS3108/TAS3108IA Memory Load Data Register (0x05)
8-BIT DATA
Datum 1 D7–D0
Datum 2 D7–D0
Datum 3 D7–D0
Datum 4 D7–D0
Datum 5 D7–D0
Datum 6 D7–D0
Datum 7 D7–D0
Datum 8 D7–D0
28-BIT DATA
0000 D27–D24
D7–D0
D15–D8
D7–D0
0000 D27–D24
D23–D16
D15–D8
D7–D0
48-BIT DATA
0000 0000
0000 0000
D47–D40
D39–D32
D31–D24
D23–D16
D15–D8
D7–D0
54-BIT DATA
0000 0000
00 D53–D48
D47–D40
D39–D32
D31–D24
D23–D16
D15–D8
D7–D0
42
I²C Register Map
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