ADS5560EVM Datasheet, PDF (42/56 Pages) Texas Instruments – 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS

ADS5560
ADS5562
SLWS207A – MAY 2008 – REVISED MAY 2012
www.ti.com
Typical LVPECL
Clock Input
Z_o
0.1mF
150W
Z_o
150W
100W
0.1mF
CLKP
CLKM
0.1mF
CMOS Clock Input
0.1mF
CLKP
VCM
CLKM
Figure 57. Typical LVPECL Clock Driving Circuit Figure 58. Typical LVCMOS Clock Driving Circuit
For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is little change in performance with a non-
50% duty cycle clock input.
Power Down
ADS556X has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.
Global STANDBY
This mode can be initiated by controlling SDATA or by setting the register bit <STBY> through the serial
interface. In this mode, the A/D converter, reference block and the output buffers are powered down resulting in
reduced total power dissipation of about 155 mW. The wake-up time from global power down to valid data is
typically 60 μs.
Output Buffer Disable
The output buffers can be disabled using OE pin in both the LVDS and CMOS modes. With the buffers disabled,
the digital outputs are three-stated. The wake-up time from this mode to data becoming valid in normal mode is
typically 700 ns in LVDS mode and 200 ns in CMOS mode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 125 mW and the wake-up time from this mode to data becoming valid in normal mode is typically 80 μs.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
Output Interface
ADS556X provides 16-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE) is provided to
power down the output buffers and put the outputs in high-impedance state.
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS or the serial interface register bit <ODI> (see Table 8).
DDR LVDS Outputs
In this mode, the 16 data bits and the output clock are put out using LVDS (Low Voltage Differential Signal)
levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in
Figure 59, so there are 8 LVDS output pairs for the data bits and 1 LVDS output pair for the output clock.
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