UCC3020 Datasheet, PDF (41/81 Pages) Texas Instruments – Digital Power Controllers

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Phase Trigger From Master DPWM
UCD3040
UCD3028
UCD3020
SLUS868H – DECEMBER 2009 – REVISED OCTOBER 2013
Event 1
1
± Cycle Adjust A
2
HR Edge
1 DPWM A
Event 2
LR Edge
Event 3
Event 4
t_P1
3
± Cycle Adjust B
4
HR Edge
DPWM B
LR Edge
t_P2
Open-Loop Mode: t_P1 = (Event 2 – Event 1) ± Cycle Adjust A
Closed-Loop Mode: t_P1 = Event 1 + CLA Duty Value + Cycle Adjust A
Open-Loop Mode: t_P2 = (Event 4 – Event 3) ± Cycle Adjust B
Closed-Loop Mode: t_P2 = Event 3 + CLA Duty Value + Cycle Adjust B
Figure 11. Multi-Output Mode – DPWM Timing Diagram
High-Resolution DPWM
The DPWM high-resolution section has DPWM edge placement capability for up to 16 phases of subclock
resolution. For the maximum 250-MHz PCLK (DPWM clock), each phase then represents 1/16 of the 4-ns
DPWM clock time, or 250 ps. The DPWM section has a disable bit and resolution-setting bits. The default
resolution setting (00) has 16 phases, and the 01 setting has eight phases (even number of phases from 0 to
15). The 10 setting uses four phases set to 0, 4, 8, and 12, whereas the 11 setting uses just the 0 and 8 phases.
So, for the maximum 250-MHz DPWM clock, the 00 setting has 250 ps resolution, the 01 setting has 500 ps
resolution, the 10 setting has 1 ns resolution, and the 11 setting has 2 ns resolution.
Oversampling
The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error
voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register
value. The oversampling register has the ability to trigger the sampling 2, 4, or 8 times per DPWM period.
DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the DPWM frequency programmed in the
period register. The interrupt can be scaled by a divided ratio of up to 255 for developing a slower interrupt
service execution loop. Table 5 outlines the divide ratios that can be programmed.
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