TRF372017_16 Datasheet, PDF (41/60 Pages) Texas Instruments – Integrated IQ Modulator PLL/VCO

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REGISTER 6 NAME
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit22
ADDR_0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
IOFF_0
IOFF_1
IOFF_2
IOFF_3
IOFF_4
IOFF_5
IOFF_6
IOFF_7
QOFF_0
QOFF_1
QOFF_2
QOFF_3
QOFF_4
QOFF_5
QOFF_6
QOFF_7
VREF_SEL_0
VREF_SEL_1
Bit23
VREF_SEL_2
Bit24
TX_DIV_SEL_0
Bit25
TX_DIV_SEL_1
Bit26
LO_DIV_SEL_0
Bit27
LO_DIV_SEL_1
Bit28
TX_DIV_BIAS_0
Bit29
TX_DIV_BIAS_1
Bit30
LO_DIV_BIAS_0
Bit31
LO_DIV_BIAS_1
TRF372017
SLWS224E – AUGUST 2010 – REVISED JANUARY 2016
Table 25. Register 6 Field Descriptions
RESET
VALUE
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
DESCRIPTION
Register address bits
Adjust Iref current used for defining I DC offset.
Full range, 2 × Iref, B[12..5] = [1 1111 111]
Mid scale, Iref B[12..5] = [1 0000 000]
Adjust Iref current used for defining Q DC offset.
Full range, 2 × Iref, B[20..13] = [1 1111 111]
Mid scale, Iref B[20..13] = [1 0000 000]
Adjust Vref in baseband common mode generation circuit.
0.65 V, B[23..21] = [000]
1 V, B[23..21] = [111]
Modulator common mode is Vref + Vbe.
Recommended programming [100]
Adjust Tx path divider.
Div1, [B25..24] = [00]
Div2, [B25..24] = [01]
Div4, [B25..24] = [10]
Div8, [B25..24] = [11]
Adjust LO path divider
Div1, [B28..27] = [00]
Div2, [B28..27] = [01]
Div4, [B28..27] = [10]
Div8, [B28..27] = [11]
TX divider bias reference current
25 µA, [B29..28] = [00]
37.5 µA, [B29..28] = [01]
50 µA, [B29..28] = [10]
62.5 µA, [B29..28] = [11]
Bias current varies directly with reference current
LO divider bias reference current
25 µA, [B29..28] = [00]
37.5 µA, [B29..28] = [01]
50 µA, [B29..28] = [10]
62.5 µA, [B29..28] = [11]
Bias current varies directly with reference current
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