TMS570LS3135 Datasheet, PDF (41/170 Pages) Texas Instruments – TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS3135, TMS570LS2135, TMS570LS2125
SPNS164C – APRIL 2012 – REVISED APRIL 2015
5.5 Switching Characteristics for Clock Domains
Over Recommended Operating Conditions
Table 5-1. Clock Domain Timing Specifications
PARAMET
ER
DESCRIPTION
CONDITIONS
MIN
f_HCLK
HCLK - System clock frequency
PGE
ZWT
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
f_GCLK
f_VCLK
f_VCLK2
GCLK - CPU clock frequency
VCLK - Primary peripheral clock frequency
VCLK2 - Secondary peripheral clock
frequency
f_VCLK3
VCLK3 - Secondary peripheral clock
frequency
f_VCLKA1
VCLKA1 - Primary asynchronous peripheral
clock frequency
f_VCLKA2
VCLKA2 - Secondary asynchronous
peripheral clock frequency
f_VCLKA4
VCLKA4 - Secondary asynchronous
peripheral clock frequency
f_RTICLK
RTICLK - clock frequency
MAX UNIT
160
50
180
50
f_HCLK
100
MHz
MHz
MHz
100 MHz
100 MHz
100 MHz
100 MHz
50 MHz
f_VCLK MHz
5.6 Wait States Required
RAM
Address Wait States
0MHz
Data Wait States
Flash
0MHz
Address Wait States
0MHz
Data Wait States
0MHz
0
0
0
0
1
2
50MHz
100MHz
Figure 5-1. Wait States Scheme
150MHz
150MHz
f_HCLK(max)
f_HCLK(max)
1
f_HCLK(max)
3
f_HCLK(max)
As shown in Figure 5-1, the TCM RAM can support program and data fetches at full CPU speed without any
address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined
mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and
180 MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait
state.
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Specifications
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