LMX2571_16 Datasheet, PDF (41/62 Pages) Texas Instruments – LMX2571 Low-Power, High-Performance PLLatinum™ RF Synthesizer

www.ti.com
LMX2571
SNAS654A – MARCH 2015 – REVISED JULY 2016
Figure 58. F1F2 Switching With SPST Switches
Figure 59. Change F1 Frequency Via SPI Programming
8.1.6 OSCin Slew Rate
A phase-lock loop consists of a clean reference clock, a PLL, and a VCO. Each of these contributes to the total
phase noise. The LMX2571 is a high-performance PLL with integrated VCO. Both PLL noise and VCO noise are
very good. Typical PLL 1/f noise and noise floor are –124 dBc/Hz and –231 dBc/Hz, respectively. To get the best
possible phase-noise performance from the device the quality of the reference clock is very important because it
may add noise to the loop. First of all, the phase noise of the reference clock must be good so that the final
performance of the system is not degraded. Furthermore, using reference clock with a rather high slew rate (such
as a square wave) is highly preferred. Driving the device input with a lower slew rate clock will degrade the
device phase noise.
For a given frequency, a sine wave clock has the slowest slew rate, especially when the frequency is low. A
CMOS clock or differential clock have much faster slew rates and are recommended. Figure 60 shows a phase-
noise comparison with different types of reference clocks. Output frequency is 480 MHz while the input clock
frequency is 26 MHz. As one can see there is a 5-dB difference in phase noise when using a clipped sine wave
TCXO compared to a differential LVPECL clock. The internal crystal oscillator of the LMX2571 performance is
also very good. If temperature compensation is not required, use crystal as the reference clock is a very good
price-performance option.
-80
Crystal
TCXO
-90
LVPECL
-100
-110
-120
-130
-140
-150
-160
10³
10⁴
10⁵
10⁶
10⁷
Offset /Hz
Figure 60. Phase Noise vs Input Clock
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: LMX2571
Submit Documentation Feedback
41