ADS5545_13 Datasheet, PDF (41/59 Pages) Texas Instruments – 14-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5545
www.ti.com
SLWS180C – NOVEMBER 2005 – REVISED MAY 2007
Power Scaling Modes
ADS5545 has a power scaling mode in which the device can be operated at reduced power levels at lower
sampling frequencies with no difference in performance. (Figure 30)⁽¹⁾ There are four power scaling modes for
different sampling frequency ranges which can be programmed using the serial interface register bits
<SCALING> (see Table 16 ). Only the AVDD power is scaled, leaving the DRVDD power unchanged.
Sampling Frequency
MSPS
> 150
105 to 150
50 to 105
< 50
Table 20. Power Scaling vs Sampling Speed
Power Scaling Mode
Default
Power Mode 1
Power Mode 2
Power Mode 3
Analog Power
(Typical)
928 mW at 170 MSPS
841 mW at 150 MSPS
670 mW at 105 MSPS
525 mW at 50 MSPS
Analog Power in Default Mode
928 mW at 170 MSPS
917 mW at 150 MSPS
830 mW at 105 MSPS
760 mW at 50 MSPS
(1) The performance in the power scaling modes is from characterization and not tested in production.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
Digital Output Information
ADS5545 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided
to power down the output buffers and put the outputs in high-impedance state.
Output Interface
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS (Table 6) or the serial interface register bit <ODI> (Table 15).
DDR LVDS Outputs
In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)
levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in
Figure 53. So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.
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