LM3S5732 Datasheet, PDF (402/825 Pages) Texas Instruments – Stellaris® LM3S5732 Microcontroller

General-Purpose Timers
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 10-4 on page 402 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is
GPTMTnMATCHR=0x411A.
Figure 10-4. 16-Bit PWM Mode Example
Count
GPTMTnR=GPTMnMR
0xC350
GPTMTnR=GPTMnMR
0x411A
TnEN set
Output
Signal
TnPWML = 0
TnPWML = 1
Time
10.4
10.4.1
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, and TIMER2 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
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November 17, 2011
Texas Instruments-Production Data