PCM1792_09 Datasheet, PDF (40/61 Pages) Texas Instruments – AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER

PCM1792
SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
www.ti.com
WDCK
(LRCK)
BCK
t(BCH)
t(BCL)
t(BCY)
t(LB)
t(BL)
50% of VDD
50% of VDD
DATA
50% of VDD
t(DS)
t(DH)
PARAMETER
t(BCY)
t(BCL)
t(BCH)
t(BL)
t(LB)
t(DS)
t(DH)
BCK pulse cycle time
BCK pulse duration, LOW
BCK pulse duration, HIGH
BCK rising edge to WDCK falling edge
WDCK falling edge to BCK rising edge
DATA setup time
DATA hold time
MIN MAX UNITS
20
ns
7
ns
7
ns
5
ns
5
ns
5
ns
5
ns
Figure 42. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the PCM1792 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15 B14 B13 B12 B11 B10 B9 B8
Register 16 R/W 0
0
1
0
0
0
0
Register 17 R/W 0
0
1
0
0
0
1
Register 18 R/W 0
0
1
0
0
1
0
Register 19 R/W 0
0
1
0
0
1
1
Register 20 R/W 0
0
1
0
1
0
0
Register 21 R/W 0
0
1
0
1
0
1
Register 22 R
0
0
1
0
1
1
0
NOTE: 1: Bit is required for selection of external digital filter mode.
−:Function is disabled. No operation even if data bit is set
B7
−
−
−
REV
−
−
−
B6
−
−
FMT2
−
SRST
−
−
B5
−
−
FMT1
−
0
−
−
B4
B3
B2
B1
B0
−
−
−
−
−
−
−
−
−
−
FMT0 −
−
−
−
OPE
− DFMS − INZD
1 MONO CHSL OS1 OS0
−
−
−
− PCMZ
−
−
− ZFGR ZFGL
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
000
001
010
Other
Audio Data Format Select
16-bit right-justified format (default)
20-bit right-justified format
24-bit right-justified format
N/A
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