TPS84250_1212 Datasheet, PDF (4/29 Pages) Texas Instruments – 7-V to 50-V Input, 2.5-A Step-Down, Integrated Power Solution

TPS84250
SLVSAR6 – AUGUST 2012
www.ti.com
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
TPS84250
RKG
UNIT
θ_JA
Junction-to-ambient thermal resistance⁽²⁾
ψ_JT
Junction-to-top characterization parameter⁽³⁾
ψ_JB
Junction-to-board characterization parameter⁽⁴⁾
41 PINS
14
3.3
6.8
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance, θ_JA, applies to devices soldered directly to a 100 mm x 100 mm double-sided, 4-layer PCB
with 1 oz. copper and natural convection cooling. Additional airflow reduces θ_JA.
(3) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature, T_J, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T_J = ψ_JT * Pdis + T_T; where Pdis is the power dissipated in the device and T_T is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T_J = ψ_JB * Pdis + T_B; where Pdis is the power dissipated in the device and T_B is
the temperature of the board 1mm from the device.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
PWRGD
VADJ
PWRGD
Logic
Thermal Shutdown
Shutdown
Logic
OCP
VIN
UVLO
TPS84250
INH/UVLO
VIN
SS/TR
STSEL
RT/CLK
AGND
+
+
VREF
Comp
OSC w/PLL
Power
Stage
and
Control
Logic
PH
VOUT
PGND
4
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