TPS5120-EP Datasheet, PDF (4/23 Pages) Texas Instruments – DUAL OUTPUT, TWO-PHASE SYNCHRONOUS BUCK DC/DC CONTROLLER

TPS5120ĆEP
DUAL OUTPUT, TWOĆPHASE SYNCHRONOUS BUCK DC/DC CONTROLLER
SGLS224A − JANUARY 2004 − REVISED APRIL 2006
Terminal Functions
TERMINAL
NAME
NO.
CT
5
FB1
2
FB2
14
GND
7
INV1
1
INV2
15
LH1
30
LH2
16
LL1
28
LL2
18
OUT1_d
27
OUT2_d
19
OUT1_u
29
OUT2_u
17
OUTGND1
26
OUTGND2
20
POWERGOOD 12
PWM/SKIP
4
REF
8
REG5V_IN
21
FLT
11
SOFTSTART1
3
SOFTSTART2 13
STBY1
9
STBY2
10
TRIP1
25
TRIP2
23
VCC
24
VREF5
22
5V_STBY
6
I/O
DESCRIPTION
I/O External capacitor from CT to GND for adjusting the triangle oscillator
O Feedback output of CH1 error amplifier
O Feedback output of CH2 error amplifier
Control GND
I Inverting input of the CH1 error amplifier, skip comparator, and OVP1/UVP1 comparator
I Inverting input of the CH2 error amplifier, skip comparator, and OVP2/UVP2 comparator
I/O Bootstrap capacitor connection for CH1 high-side gate drive
I/O Bootstrap capacitor connection for CH2 high-side gate drive
I/O Bootstrap this pin low for CH1 high-side gate driving return and output current protection. Connect this pin to
the junction of the high-side and low-side FETs for a floating drive configuration.
I/O Bootstrap this pin low for CH2 high-side gate driving return and output current protection. Connect this pin to
the junction of the high-side and low-side FETs for a floating drive configuration.
O Gate drive output for CH1 low-side gate drive
O Gate drive output for CH2 low-side gate drive
O Gate drive output for CH1 high-side switching FETs
O Gate drive output for CH2 high-side switching FETs
Ground for CH1 FET drivers
Ground for CH2 FET drivers
O Power good open-drain output. When low, POWERGOOD reports an output fail condition. PG comparators
monitor both SMPS’s over voltage and UVLO of VREF5. The threshold is ±7%. When the SMPS starts up, the
POWERGOOD pin’s output goes high. POWERGOOD also monitors VREF5’s UVLO output.
I PWM/SKIP mode select pin. The PWM/SKIP pin is used to change the output’s operating mode. If this terminal
is lower than 0.5 V, it works in PWM mode. When a minimum voltage of 2 V is applied, the device operates in
skip mode. In light load condition (< 0.2 A), the skip mode gives a short pulse to the low-side FETs instead of a
full pulse. With this control, switching frequency is lowered and switching loss is reduced. Also, the output
capacitor energy discharging through the output inductor and low-side FETs is stopped. Therefore, TPS5120
achieves a higher efficiency in light load conditions.
O 0.85-V reference voltage output. The 0.85-V reference voltage is used for setting the output voltage and the
voltage protection. This reference voltage is dropped down from a 5-V regulator.
I External 5-V input
I/O Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time up.
I/O External capacitor from SOFTSTART1 to GND for CH1 softstart control. Separate soft-start terminals make it
possible to set the start-up time of each output independently.
I/O External capacitor from SOFTSTART2 to GND for CH2 softstart control. Separate soft-start terminals make it
possible to set the start-up time of each output independently.
I Standby control for CH1. SMPS1 can be switched into standby mode separately by grounding the STBY1 pin.
I Standby control for CH2. SMPS2 can be switched into standby mode separately by grounding the STBY2 pin.
I External resistor connection for CH1 output current control
I External resistor connection for CH2 output current control
Supply voltage input
O 5-V internal regulator output
I 5-V linear regulator control
4
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