TPS3808-EP Datasheet, PDF (4/15 Pages) Texas Instruments – LOW QUIESCENT CURRENT, PROGRAMMABLE DELAY SUPERVISORY CIRCUIT

TPS3808-EP
SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 ................................................................................................................................................. www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
MR
SENSE
V_DD
V_DD
TPS3808G01
Adjustable Voltage
90k
RESET
V_DD
V_DD
90k
MR
Reset
Logic
Timer
−
+
C_T
0.4V
V_REF
GND
Adjustable Voltage Version
SENSE
R₁
−
+
R₂
R₁ + R₂ = 4MΩ
Reset
Logic
Timer
0.4V
V_REF
GND
Fixed Voltage Version
Figure 1. Adjustable and Fixed Voltage Versions
RESET
C_T
PIN ASSIGNMENTS
DBV PACKAGE
SOT23
(TOP VIEW)
RESET 1
GND 2
MR 3
6
V_DD
5
SENSE
4
C_T
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
SOT23 (DBV)
PIN NO. DESCRIPTION
RESET
GND
1
RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the
SENSE input is lower than the threshold voltage (V_IT) or the MR pin is set to a logic low). RESET remains
low (asserted) for the reset period after both SENSE is above V_IT and MR is set to a logic high. A pullup
resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher
than V_DD.
2
Ground
MR
3
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to V_DD by a 90kΩ pullup resistor.
C_T
4
Reset period programming pin. Connecting this pin to V_DD through a 40-kΩ to 200-kΩ resistor or leaving it
open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced
capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section
for more information.
SENSE
V_DD
5
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage V_IT, then RESET is asserted.
6
Supply voltage. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
4
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