TP3052-X Datasheet, PDF (4/20 Pages) Texas Instruments – TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family

Symbol
MCLK_X
FS_X
BCLK_X
D_X
TS_X
GS_X
VF_XI^−
VF_XI⁺
Function
Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK_R. Best
performance is realized from
synchronous operation.
Transmit frame sync pulse input which
enables BCLK_X to shift out the PCM data
on D_X. FS_X is an 8 kHz pulse train, see
Figure 2 and Figure 3 for timing details.
The bit clock which shifts out the PCM
data on D_X. May vary from 64 kHz to 2.048
MHz, but must be synchronous with
MCLK_X.
The TRI-STATE^® PCM data output which
is enabled by FS_X.
Open drain output which pulses low
during the encoder time slot.
Analog output of the transmit input
amplifier. Used to externally set gain.
Inverting input of the transmit input
amplifier.
Non-inverting input of the transmit input
amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializes
the COMBO and places it into a power-down state. All non-
essential circuits are deactivated and the D_X and VF_RO out-
puts are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK_R/PDN pin and FS_X and/or FS_R pulses must be present.
Thus, 2 power-down control modes are available. The first is
to pull the MCLK_R/PDN pin high; the alternative is to hold both
FS_X and FS_R inputs continuously low—the device will power-
down approximately 1 ms after the last FS_X or FS_R pulse.
Power-up will occur on the first FS_X or FS_R pulse. The TRI-
STATE PCM data output, D_X, will remain in the high
impedance state until the second FS_X pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive direc-
tions. In this mode, a clock must be applied to MCLK_X and the
MCLK_R/PDN pin can be used as a power-down control. A low
level on MCLK_R/PDN powers up the device and a high level
powers down the device. In either case, MCLK_X will be se-
lected as the master clock for both the transmit and receive
circuits. A bit clock must also be applied to BCLK_X and the
BCLK_R/CLKSEL can be used to select the proper internal di-
vider for a master clock of 1.536 MHz, 1.544 MHz or 2.048
MHz. For 1.544 MHz operation, the device automatically com-
pensates for the 193rd clock pulse each frame.
With a fixed level on the BCLK_R/CLKSEL pin, BCLK_X will be
selected as the bit clock for both the transmit and receive di-
rections. Table 1 indicates the frequencies of operation which
can be selected, depending on the state of BCLK_R/CLKSEL.
In this synchronous mode, the bit clock, BCLK_X, may be from
64 kHz to 2.048 MHz, but must be synchronous with
MCLK_X.
Each FS_X pulse begins the encoding cycle and the PCM data
from the previous encode cycle is shifted out of the enabled
D_X output on the positive edge of BCLK_X. After 8 bit clock
periods, the TRI-STATE D_X output is returned to a high
impedance state. With an FS_R pulse, PCM data is latched via
the D_R input on the negative edge of BCLK_X (or BCLK_R if run-
ning). FS_X and FS_R must be synchronous with MCLK_X/R.
TABLE 1. Selection of Master Clock Frequencies
BCLK_R/CLKSEL
Master Clock
Frequency Selected
TP3057
TP3054
Clocked
0
1
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK_X and MCLK_R must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmission
performance, however, MCLK_R should be synchronous with
MCLK_X, which is easily achieved by applying only static logic
levels to the MCLK_R/PDN pin. This will automatically connect
MCLK_X to all internal MCLK_R functions (see Pin Description).
For 1.544 MHz operation, the device automatically compen-
sates for the 193rd clock pulse each frame. FS_X starts each
encoding cycle and must be synchronous with MCLK_X and
BCLK_X. FS_R starts each decoding cycle and must be syn-
chronous with BCLK_R. BCLK_R must be a clock, the logic levels
shown in Table 1 are not valid in asynchronous mode.
BCLK_X and BCLK_R may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS_X and FS_R, must be one bit clock period long, with
timing relationships specified in Figure 2. With FS_X high dur-
ing a falling edge of BCLK_X, the next rising edge of BCLK_X
enables the D_X TRI-STATE output buffer, which will output
the sign bit. The following seven rising edges clock out the
remaining seven bits, and the next falling edge disables the
D_X output. With FS_R high during a falling edge of BCLK_R
(BCLK_X in synchronous mode), the next falling edge of
BCLK_R latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. All four devices may
utilize the short frame sync pulse in synchronous or asyn-
chronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FS_X and FS_R, must be three or more bit clock periods long,
with timing relationships specified in Figure 3. Based on the
transmit frame sync, FS_X, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a mini-
mum of 160 ns. The D_X TRI-STATE output buffer is enabled
with the rising edge of FS_X or the rising edge of BCLK_X,
whichever comes later, and the first bit clocked out is the sign
bit. The following seven BCLK_X rising edges clock out the re-
maining seven bits. The D_X output is disabled by the falling
3
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