TMS320TEST Datasheet, PDF (4/8 Pages) Texas Instruments – DVCPro50 Decoder (v01.01.00) on TMS320C6678

DVCPro50 Decoder (v01.01.00) on TMS320C6678
SPRS807 – NOVEMBER 2011
TC Q
TC 0
Table 6.
TC 1
EDMA Configuration
TC 2
TC 3
TOTAL
MAXIMUM(1)
Usage
Not Used
Not Used
Writes to
DDR
Writes to L2
-
-
Priority(2)
-
EDMA Channels
-
QDMA Channels
-
Num PARAMS
-
-
2
2
-
-
-
3
1
4
64
-
0
0
0
0
-
15
1
16
256
Notes:
1.
2.
Lesser number corresponds to higher TC priority. Default priority is 2. When different TC’s have same priority, the
arbitration order is TC0 > TC1 > TC2 > TC3.
Max corresponds to the maximum number of EDMA/QDMA channels or maximum number of PARAMS available on
the chip. It does NOT indicate the maximum number requested by the codec.
4