TLV5590_08 Datasheet, PDF (4/16 Pages) Texas Instruments – 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEX

TLV5590
2ĆBIT ANALOGĆTOĆDIGITAL CONVERTER
FOR FLEXt PAGER CHIPSET
SLAS134B − NOVEMBER 1995 − REVISED NOVEMBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†
Supply voltage range, AV_DD, DV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, V_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV_DD + 0.3 V
Output voltage range, EXTS0, EXTS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV_DD + 0.3 V
Offset input voltage, V_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV_DD + 0.3 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, AVDD, DVDD
Power supply ripple
Input clock frequency, f(CLK)
Input clock duty cycle
Voltage offset applied at DC OFFSET, VI(DC _OFFSET) (see Notes 1 and 2)
Analog input voltage, VI(pp) (See Notes 1 and 2) VDD = 3.1 V
High-level control input voltage, VIH
VDD = 2.7 V to 3.3 V
Low-level control input voltage, VIL
VDD = 2.7 V to 3.3 V
Operating free-air temperature, TA
MIN
2.7
45
0.25
0.25
0.8 DVDD
−25
NOM MAX
3.3
0.002
38.4
50
55
VDD−0.25
VDD − 0.25
0.2 DVDD
85
UNIT
V
Vpp
kHz
%
V
Vpp
V
V
°C
NOTES: 1. VI(OFFSET) =VQ − VI(DC _OFFSET) where VQ is the dc quiescent voltage of the signal applied to the SIG terminal.
NOTES: 2.
VI(PEAK)
ǒ Ǔ VDD
2
*
0.25 V
+
4.217
* VI(OFFSET)_{*80 mV}
The pass-band filter gain represents the maximum specified voltage gain in volts/volt of the filter. The maximum gain for the filter
is 4.217 V/V (12.5 dB). The input voltage range from this equation defines the maximum allowable input signal at the SIG terminal
with a given voltage, VI(DC _OFFSET), applied at the DC OFFSET terminal and a quiescent dc input voltage, VQ, of the signal applied
at the SIG terminal. When the input voltage is within this range, the peak and valley DACs do not over range. The 80 mV value is
the tolerance on the voltage output at the MID terminal.
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