TLK4015_09 Datasheet, PDF (4/26 Pages) Texas Instruments – QUAB 0.6 to 1.5 Gbps TRANSCEIVER

TLK4015
QUAD 0.6 to 1.5 Gbps TRANSCEIVER
SLLS541B − DECEMBER 2002 − REVISED JULY 2006
block diagram
A detailed block diagram of each channel is shown below. Channels A, B, C, and D are identical and are
configured as four separate links.
LOOPENx
PRBSENx
Tx_EN
Tx_ER
PRBS
Generator
10
PRBSEN
DOUTTxP
DOUTTxN
2:1
MUX
10
Parallel to
Serial
8
10
10
BIAS
RREFx
TDx[0−15]
MUX
8
10
Bit
Clock
GTx_CLK
TESTENx
ENABLEx
Controls:
PLL,Bias,Rx,
Tx
Multiplying
Clock
Synthesizer
Bit
Clock
PRBSENx
Rx_ER
PRBS_PASSx
2:1
MUX
Interpolator and
Clock Recovery
2:1
MUX
Rx_CLK
Rx_DV/LOSx
RDx[0−15]
PRBSEN
Comma
Detect
8 _{and 8b/10b} 10
Decoding
Comma
8
Detect
10
and 8b/10b
Decoding
PRBS
Verification
Recovered
Clock
1:2
MUX
10
Serial to
Parallel
2:1 ^Data
MUX
Signal Detect
(LOS)
DINRxP
DINRxN
4
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