TAS3108 Datasheet, PDF (4/63 Pages) Texas Instruments – AUDIO DIGITAL SIGNAL PROCESSORS

Not Recommended for New Designs
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
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2.2 Power Supply
The power supply contains supply regulators that provide analog and digital regulated power for various
sections of the TAS3108/TAS3108IA. Only one external 3.3-V supply is required. All other voltages are
generated on-chip from the external 3.3-V supply.
2.3 Clock Control
The TAS3108/TAS3108IA can be an audio data clock-master or clock-slave device. In clock-master mode,
it generates MCLK, SCLK, and LRCLK. In clock-slave mode, it accepts MCLK, SCLK, and LRCLK. It can
generate or accept master clocks from 6 MHz to 24.576 MHz. Master or slave operation is set via I²C
register 0x00. The TAS3108/TAS3108IA can use a 6-MHz to 20-MHz crystal or a 6-MHz to 24.576-MHz,
3.3-V MCLKI digital input as the master clock in either clock-master or clock-slave mode. In clock-slave
mode, the master clock frequency does not need to be an integer multiple of the sample rate.
The TAS3108/TAS3108IA does not support clock error detection. If a clock error occurs, the
TAS3108/TAS3108IA does not prevent invalid data or clocks from being output. This means that the
application system must be designed to handle clock errors.
2.4 Serial Audio Ports (SAPs)
Serial audio data is input via pins SDIN1, SDIN2, SDIN3, and SDIN4. Serial audio data is output on pins
SDOUT1, SDOUT2, SDOUT3, and SDOUT4. The TAS3108/TAS3108IA accepts 32-, 44.1-, 48-, 88.2-,
96-, 176.4-, or 192-kHz serial data as 16-, 20-, 24-, or 32-bit data in left justified, right justified, or I²S serial
data formats. All four ports accommodate these three 2 channel data formats.
In addition to supporting the 2 channel formats, SDIN1 and SDOUT1 also provide support for time-division
multiplex (TDM) data formats of 4, 6, or 8 channels. The data formats are selectable via I²C register 0x00.
All input channels must use the same data format. All output channels must use the same data format.
However, the input and output formats can be different.
2.5 M8051Warp Microprocessor
The M8051Warp (8051) microprocessor controls I²C reads and writes and participates in some audio
processing tasks requiring multiframe (f_S period) processing cycles. The 8051 processor performs some
control calculations and exchanges data between the audio DSP core and the I²C interface. It also
provides mode control for the SAP interface and clock control. The microcode can program the GPIO pin
for post-boot-up operation to be an input or an output. For more information, see the TAS3108/TAS3108IA
Firmware Programmer's Guide (SLEU067).
2.6 I²C Control Interface
The TAS3108/TAS3108IA has an I²C slave-only interface (SDA1 and SCL1) for receiving commands and
providing status to the system controller, and a separate master I²C interface (SDA2 and SCL2) to
download programs and data from external memory such as an EEPROM. See Section 6 for more
information.
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Functional Description
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