SN74LVC1G07-Q1 Datasheet, PDF (4/11 Pages) Texas Instruments – SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT

SN74LVC1G07-Q1
SCES826 – MARCH 2011
From Output
Under Test
C_L
(see Note A)
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
R_L
R_L
V_LOAD
S1
Open
GND
TEST
t_PZL (see Notes E and F)
t_PLZ (see Notes E and G)
t_PHZ/t_PZH
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S1
V_LOAD
V_LOAD
V_LOAD
LOAD CIRCUIT
V_CC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
INPUT
V_I
t_r/t_f
V_CC
≤ 2 ns
V_CC
≤ 2 ns
3V
≤ 2.5 ns
V_CC
≤ 2.5 ns
V_M
V_CC/2
V_CC/2
1.5 V
V_CC/2
V_LOAD
2 × V_CC
2 × V_CC
6V
2 × V_CC
C_L
30 pF
30 pF
50 pF
50 pF
R_L
1 kΩ
500 Ω
500 Ω
500 Ω
V_∆
0.15 V
0.15 V
0.3 V
0.3 V
Input
t_w
V_M
V_M
VOLTAGE WAVEFORMS
PULSE DURATION
Timing Input
V_I
Data Input
0V
V_I
V_M
0V
t_su
t_h
V_I
V_M
V_M
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
V_I
V_M
V_M
0V
Output
Control
V_M
V_M
V_I
0V
t_PLH
Output
V_M
t_PHL
V_M
V_OH
V_OL
t_PHL
t_PLH
Output
V_OH
V_M
V_M
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 1
S1 at V_LOAD
(see Note B)
Output
Waveform 2
S1 at V_LOAD
(see Note B)
t_PZL
V_M
t_PZH
V_M
t_PLZ
V_LOAD/2
V_OL + V_∆
V_OL
t_PHZ
V_LOAD/2
V_LOAD/2 − V_∆
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t_PLZ and t_PZL are the same as t_pd.
F. t_PZL is measured at V_M.
G. t_PLZ is measured at V_OL + V_∆.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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