LMC7221_14 Datasheet, PDF (4/21 Pages) Texas Instruments – LMC7221 Tiny CMOS Comparator with Rail-To-Rail Input and Open Drain Output

LMC7221
SNOS748E – SEPTEMBER 1999 – REVISED MARCH 2013
www.ti.com
5.0V and 15.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for T_J = 25°C, V⁺ = 5.0V and 15V, V^− = 0V, V_CM = V_O = V⁺/2. Boldface limits
apply at the temperature extremes.
Parameter
I_SC
Short Circuit Current
Test Conditions
Sinking ⁽⁴⁾
Typ ⁽¹⁾
45
LMC7221AI
Limit ⁽²⁾
LMC7221BI
Limit ⁽²⁾
Units
mA
(4) Limiting input pin current is only necessary for input voltages which exceed the absolute maximum input voltage rating.
Leakage Characteristics
T_J = 25°C
Parameter
I_LEAKAGE Output Leakage Current
Test Conditions
V⁺ = 2.7V
V_IN(+) = 0.5V
V_IN(−) = 0V
V_OUT = 15V
Typ ⁽¹⁾
0.1
LMC7221AI
Limit ⁽²⁾
LMC7221BI
Limit ⁽²⁾
500
500
Units
nA
(1) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(2) All limits are specified by testing or statistical analysis.
AC Electrical Characteristics
Unless otherwise specified, all limits ensured for T_J = 25°C, V⁺ = 5V, V^− = 0V, V_CM = V_O = V⁺/2. Boldface limits apply at the
temperature extreme.
Parameter
t_rise
Rise Time
t_fall
Fall Time
Test Conditions
f = 10 kHz, C_L = 50 pF, ⁽³⁾
Overdrive = 10 mV, 5 kΩ Pullup
f = 10 kHz, C_L = 50 pF, ⁽³⁾
Overdrive = 10 mV, 5 kΩ Pullup
Typ ⁽¹⁾
0.3
0.3
LMC7221AI LMC7221BI
Limit ⁽²⁾
Limit ⁽²⁾
Units
μs
μs
t_PHL
Propagation Delay
(High to Low) ⁽⁴⁾
f = 10 kHz, C_L = 50 pF,
10 mV
10
5 kΩ Pullup ⁽³⁾
100 mV
4
μs
V⁺ = 2.7V, f = 10 kHz,
10 mV
10
C_L = 50 pF, 5 kΩ Pullup ⁽³⁾ _{100 mV}
4
μs
t_PLH
Propagation Delay
(Low to High) ⁽⁴⁾
f = 10 kHz, C_L = 50 pF,
10 mV
6
5 kΩ Pullup ⁽³⁾
100 mV
4
μs
V⁺ = 2.7V, f = 10 kHz,
10 mV
7
C_L = 50 pF, 5 kΩ Pullup ⁽³⁾ _{100 mV}
4
μs
(1) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(2) All limits are specified by testing or statistical analysis.
(3) Do not short circuit the output to V⁺ when V⁺ is greater than 12V or reliability will be adversely affected.
(4) Input offset voltage average drift is calculated by dividing the accelerated operating life V_OS drift by the equivalent operational time. This
represents worst case input conditions and includes the first 30 days of drift.
4
Submit Documentation Feedback
Product Folder Links: LMC7221
Copyright © 1999–2013, Texas Instruments Incorporated