LF198-N Datasheet, PDF (4/15 Pages) Texas Instruments – LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits

Electrical Characteristics
The following specifcations apply for −V_S + 3.5V ≤ V_IN ≤ +V_S − 3.5V, +V_S = +15V, −V_S = −15V, T_A = T_j = 25˚C, C_h = 0.01 µF,
R_L = 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
Parameter
Conditions
LF198A
LF398A
Units
Min Typ Max Min Typ Max
Input Impedance
Gain Error
T_j = 25˚C
T_j = 25˚C, R_L = 10k
Full Temperature Range
10¹⁰
0.002
0.005
0.01
10¹⁰
Ω
0.004 0.005 %
0.01 %
Feedthrough Attenuation Ratio
at 1 kHz
T_j = 25˚C, C_h = 0.01 µF
86 96
86 90
dB
Output Impedance
T_j = 25˚C, “HOLD” mode
Full Temperature Range
0.5
1
4
0.5
1
Ω
6
Ω
“HOLD” Step, (Note 6)
Supply Current, (Note 5)
Logic and Logic Reference Input
Current
T_j = 25˚C, C_h = 0.01µF, V_OUT = 0
T_j≥25˚C
T_j = 25˚C
0.5
1
4.5 5.5
2
10
1.0
1
mV
4.5 6.5 mA
2
10 µA
Leakage Current into Hold
Capacitor (Note 5)
T_j = 25˚C, (Note 7)
Hold Mode
30 100
30 100 pA
Acquisition Time to 0.1%
Hold Capacitor Charging Current
Supply Voltage Rejection Ratio
Differential Logic Threshold
∆V_OUT = 10V, C_h = 1000 pF
C_h = 0.01 µF
V_IN−V_OUT = 2V
V_OUT = 0
T_j = 25˚C
4
6
4
6
µs
20
25
20
25
µs
5
5
mA
90 110
90 110
dB
0.8 1.4
2.4 0.8 1.4 2.4
V
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX, θ_JA, and the ambient temperature, T_A. The maximum
allowable power dissipation at any temperature is P_D = (T_JMAX − T_A)/θ_JA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum
junction temperature, T_JMAX, for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C.
Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the nega-
tive supply.
Note 4: See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices.
Note 5: These parameters guaranteed over a supply voltage range of ±5 to ±18V, and an input range of −V_S + 3.5V ≤ V_IN ≤ +V_S − 3.5V.
Note 6: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step
with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.
Note 7: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range.
Note 8: A military RETS electrical test specification is available on request. The LF198 may also be procured to Standard Military Drawing #5962-8760801GA or to
MIL-STD-38510 part ID JM38510/12501SGA.
Typical Performance Characteristics
Aperture Time
(Note 9)
Dielectric Absorption
Error in Hold Capacitor
Dynamic Sampling Error
DS005692-17
Note 9: See Definition of Terms
DS005692-18
3
DS005692-19
www.national.com