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ISO7421E-Q1 Datasheet, PDF (4/18 Pages) Texas Instruments – Low-Power Dual Digital Isolators
ISO7421E-Q1
SLLSEA5B – MARCH 2012 – REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
VOH
High-level output voltage
IOH = –4 mA; See Figure 1
IOH = –20 µA; See Figure 1
VCC –0.8
VCC –0.1
VOL
Low-level output voltage
IOL = 4 mA; See Figure 1
IOL = 20 µA; See Figure 1
VI(HYS) Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
INx at 0 V or VCC
–10
CMTI Common-mode transient immunity VI = VCC or 0 V; See Figure 3
25
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ISO7420x
ICC1
DC to 1 Mbps DC Input: VI = VCC or 0 V
ICC2
AC Input: CL = 15 pF
ICC1
10 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
25 Mbps
ICC2
CL = 15 pF
ICC1
ICC2
50 Mbps
ISO7421x
ICC1
DC to 1 Mbps DC Input: VI = VCC or 0 V
ICC2
AC Input: CL = 15 pF
ICC1
10 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
25 Mbps
ICC2
CL = 15 pF
ICC1
ICC2
50 Mbps
TYP
4.6
5
0.2
0
400
50
0.4
3.4
0.6
4.5
1
6.2
1.7
9
2.3
2.3
2.9
2.9
4.3
4.3
6
6
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MAX UNIT
V
0.4
V
0.1
mV
10 µA
µA
kV/µs
0.8
5
1
6
mA
1.5
8
2.5
12
3.6
3.6
4.5
4.5
mA
6
6
9.1
9.1
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
tPLH, tPHL
PWD (1)
tsk(pp)
tsk(o)
tr
tf
tfs
Propagation delay time
See Figure 1
Pulse width distortion |tPHL – tPLH|
Part-to-part skew time
Channel-to-channel output skew time
Output signal rise time
See Figure 1
Output signal fall time
Fail-safe output delay time from input power loss See Figure 2
(1) Also known as pulse skew.
MIN TYP MAX UNIT
9
14 ns
0.3
3.7 ns
4.9 ns
3.6 ns
1
ns
1
ns
6
µs
4
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