DS90C383B_15 Datasheet, PDF (4/17 Pages) Texas Instruments – Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

DS90C383B
SNLS177G – APRIL 2004 – REVISED APRIL 2013
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Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12)⁽¹⁾
f = 40 MHz
Min
Typ
Max
Unit
-0.25
0
+0.25
ns
TPPos1 Transmitter Output Pulse Position for Bit 1
3.32
3.57
3.82
ns
TPPos2 Transmitter Output Pulse Position for Bit 2
6.89
7.14
7.39
ns
TPPos3 Transmitter Output Pulse Position for Bit 3
10.46
10.71
10.96
ns
TPPos4 Transmitter Output Pulse Position for Bit 4
14.04
14.29
14.54
ns
TPPos5 Transmitter Output Pulse Position for Bit 5
17.61
17.86
18.11
ns
TPPos6 Transmitter Output Pulse Position for Bit 6
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12)⁽¹⁾
f = 25MHz
21.18
21.43
21.68
ns
-0.45
0
+0.45
ns
TPPos1 Transmitter Output Pulse Position for Bit 1
5.26
5.71
6.16
ns
TPPos2 Transmitter Output Pulse Position for Bit 2
10.98
11.43
11.88
ns
TPPos3 Transmitter Output Pulse Position for Bit 3
16.69
17.14
17.59
ns
TPPos4 Transmitter Output Pulse Position for Bit 4
22.41
22.86
23.31
ns
TPPos5 Transmitter Output Pulse Position for Bit 5
25.12
28.57
29.02
ns
TPPos6 Transmitter Output Pulse Position for Bit 6
33.84
34.29
34.74
ns
TSTC TxIN Setup to TxCLK IN (Figure 7)
2.5
ns
THTC TxIN Hold to TxCLK IN (Figure 7)
0.5
ns
TCCD
TxCLK IN to TxCLK OUT Delay (Figure 8) 50% duty cycle input clock is assumed,
T_A= -10°C, and 65MHz for "Min", T_A= 70°C,and 25MHz for "Max", V_CC= 3.6V,
R_FB = V_CC
TxCLK IN to TxCLK OUT Delay (Figure 8) 50% duty cycle input clock is assumed,
T_A= -10°C, and 65MHz for "Min", T_A= 70°C, and 25MHz for "Max", V_CC= 3.6V,
R_FB = GND
3.340
3.011
7.211
ns
6.062
ns
SSCG
f = 25MHz
100kHz ±
2.5%/-5%
Spread Spectrum Clock support; Modulation frequency with a f = 40MHz
linear profile⁽²⁾.
100kHz ±
2.5%/-5%
f = 65MHz
100kHz ±
2.5%/-5%
TPLLS Transmitter Phase Lock Loop Set (Figure 9)
10
ms
TPDD Transmitter Power Down Delay (Figure 11)
100
ns
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK- pins.
AC Timing Diagrams
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
B. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Figure 2. “Worst Case” Test Pattern
4
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