DS90C363_13 Datasheet, PDF (4/19 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link–65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link–65 MHz

DS90C363, DS90CF364
SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time (Figure 6 )
0.75
LHLT
LVDS High-to-Low Transition Time (Figure 6 )
0.75
TCIT
TxCLK IN Transition Time (Figure 8 )
TCCS
TxOUT Channel-to-Channel Skew (Figure 9 )
250
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 20 )
f = 65 MHz
−0.4
0
TPPos1 Transmitter Output Pulse Position for Bit 1
1.8
2.2
TPPos2 Transmitter Output Pulse Position for Bit 2
4.0
4.4
TPPos3 Transmitter Output Pulse Position for Bit 3
6.2
6.6
TPPos4 Transmitter Output Pulse Position for Bit 4
8.4
8.8
TPPos5 Transmitter Output Pulse Position for Bit 5
10.6
11.0
TPPos6 Transmitter Output Pulse Position for Bit 6
12.8
13.2
TCIP
TxCLK IN Period (Figure 10)
15
T
TCIH
TxCLK IN High Time (Figure 10)
0.35T
0.5T
TCIL
TxCLK IN Low Time (Figure 10)
0.35T
0.5T
TSTC
TxIN Setup to TxCLK IN (Figure 10 )
f = 65 MHz
2.5
THTC
TxIN Hold to TxCLK IN (Figure 10 )
0
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay at 25°C, V_CC = 3.3V (Figure 12 )
Transmitter Phase Lock Loop Set (Figure 14 )
3.0
3.7
TPDD
Transmitter Power Down Delay (Figure 18 )
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Max
Unit
1.5
ns
1.5
ns
5
ns
ps
0.3
ns
2.5
ns
4.7
ns
6.9
ns
9.1
ns
11.3
ns
13.5
ns
50
ns
0.65T
ns
0.65T
ns
ns
ns
5.5
ns
10
ms
100
ns
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 7 )
2.2
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 7 )
2.2
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 21 )
f = 65 MHz
0.7
1.1
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
3.3
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
5.5
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
7.7
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
9.9
RSPos5 Receiver Input Strobe Position for Bit 5
11.7
12.1
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin ⁽¹⁾ (Figure 22 )
f = 65 MHz
13.9
14.3
400
RCOP
RxCLK OUT Period (Figure 11)
15
T
RCOH
RxCLK OUT High Time (Figure 11 )
f = 65 MHz
7.3
8.6
RCOL
RxCLK OUT Low Time (Figure 11)
f = 65 MHz
3.45
4.9
RSRC
RxOUT Setup to RxCLK OUT (Figure 11 )
f = 65 MHz
2.5
6.9
RHRC
RxOUT Hold to RxCLK OUT (Figure 11 )
f = 65 MHz
2.5
5.7
RCCD
RPLLS
RxCLK IN to RxCLK OUT Delay at 25°C, V_CC = 3.3V (Figure 13 )
Receiver Phase Lock Loop Set (Figure 15 )
5.0
7.1
RPDD
Receiver Power Down Delay (Figure 19 )
Max
Unit
5.0
ns
5.0
ns
1.4
ns
3.6
ns
5.8
ns
8.0
ns
10.2
ns
12.4
ns
14.6
ns
ps
50
ns
ns
ns
ns
ns
9.0
ns
10
ms
1
µs
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
4
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