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DS7831_11 Datasheet, PDF (4/13 Pages) Texas Instruments – Dual TRI-STATE Line Driver | |||
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
â65ËC to +150ËC
Lead Temperature (Soldering, 4 sec.)
260ËC
Maximum Power Dissipation (Note 1) at 25ËC
Cavity Package
1433 mW
Molded Package
1362 mW
Operating Conditions
Min
Max
Units
Supply Voltage (VCC)
DS7831
4.5
5.5
V
DS8831/DS8832
4.75
5.25
V
Temperature (TA)
DS7831
â55
+125
ËC
DS8832
0
+70
ËC
Note 1: Derate cavity package 9.6 mW/ËC above 25ËC; derate molded pack-
age 10.9 mW/ËC above 25ËC.
Electrical Characteristics (Notes 3, 4)
Symbol
VIH
VIL
VOH
Parameter
Logical â1â Input Voltage
Logical â0â Input Voltage
Logical â1â Output Voltage
VOL
Logical â0â Output Voltage
IIH
Logical â1â Input Current
IIL
IOD
ISC
ICC
VCLI
VCLO
Logical â0â Input Current
Output Disable Current
Output Short Circuit Current
Supply Current
Input Diode Clamp Voltage
Output Diode Clamp
Voltage
Conditions
VCC = Min
VCC = Min
DS7831
IO = â40 mA
VCC = Min
IO = â2 mA
DS8832
IO = â40 mA
IO = â5.2 mA
DS7831
IO = 40 mA
VCC = Min
IO = 32 mA
DS8832
IO = 40 mA
IO = 32 mA
VCC = Max
DS7831, VIN = 5.5V
DS8832, VIN = 2.4V
VCC = Max, VIN = 0.4V
VCC = Max, VO = 2.4V or 0.4V
VCC = Max, (Note 5)
VCC = Max in TRI-STATE
VCC = 5.0V, TA = 25ËC, IIN = â12 mA
VCC = 5.0V,
IOUT = â12 mA DS7831
TA = 25ËC
DS8832
IOUT = 12 mA
DS7831
Min Typ
2.0
1.8 2.3
2.4 2.7
1.8 2.5
2.4 2.9
0.29
0.29
â1.0
â40
â40 â100
65
Max
0.8
0.50
0.40
0.50
0.40
1
40
â1.6
40
â120
90
â1.5
â1.5
Units
V
V
V
V
V
V
V
V
V
V
mA
µA
mA
µA
mA
mA
V
V
VCC + 1.5 V
Switching Characteristics
TA = 25ËC, VCC = 5V, unless otherwise noted
Symbol
Parameter
tpd0
Propagation Delay to a Logical â0â
from Inputs A1, A2, B1, B2
Differential Single-ended Mode
Control to Outputs
tpd1
Propagation Delay to a Logical â1â
from Inputs A1, A2, B1, B2
Differential Single-ended Mode
Control to Outputs
t1H
Delay from Disable Inputs to High
Impedance State (from Logical â1â
Level)
t0H
Delay from Disable Inputs to High
Impedance State (from Logical â0â Level)
Conditions
Min
(See Figure 4 and Figure 5 )
Typ Max
13
25
13
25
6
12
14
22
Units
ns
ns
ns
ns
3
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