DRV8844 Datasheet, PDF (4/17 Pages) Texas Instruments – QUAD 1/2-H-BRIDGE DRIVER IC

DRV8844
SLVSBA2 – JULY 2012
CP1 1
CP2 2
VCP 3
VM 4
OUT1 5
VNEG 6
OUT2 7
OUT3 8
VNEG 9
OUT4 10
VM 11
NC 12
NC 13
VNEG 14
GND
(PPAD)
28 VNEG
27 IN1
26 EN1
25 IN2
24 EN2
23 IN3
22 EN3
21 IN4
20 EN4
19 LGND
18 nFAULT
17 nSLEEP
16 nRESET
15 V3P3OUT
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) ^{(1) (2)}
VALUE
VM
Power supply voltage range
–0.3 to 65
Logic ground voltage range (LGND)
–0.5 to VM - 8
Digital pin voltage range
LGND - 0.5 to LGND + 7
Peak motor drive output current, t < 1 μS
Continuous motor drive output current⁽³⁾
Internally limited
2.5
T_J
Operating virtual junction temperature range
T_stg
Storage temperature range
–40 to 150
–60 to 150
UNIT
V
V
V
A
A
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VNEG terminal, unless otherwise specified.
(3) Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
DRV8844
PWP
16 PINS
31.6
15.9
5.6
0.2
5.5
1.4
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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