DRV8802 Datasheet, PDF (4/18 Pages) Texas Instruments – DC MOTOR DRIVER IC

DRV8802
SLVSAM9A – APRIL 2011 – REVISED JUNE 2011
PWP PACKAGE
(TOP VIEW)
CP1 1
CP2 2
VCP 3
VMA 4
AOUT1 5
ISENA 6
AOUT2 7
BOUT2 8
ISENB 9
BOUT1 10
VMB 11
AVREF 12
BVREF 13
GND 14
GND
(PPAD )
28 GND
27 BI1
26 BI0
25 AI1
24 AI0
23 BPHASE
22 BENBL
21 AENBL
20 APHASE
19 DECAY
18 nFAULT
17 nSLEEP
16 nRESET
15 V3P3OUT
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}
VMx
VREF
T_J
T_A
T_stg
Power supply voltage range
Digital pin voltage range
Input voltage
ISENSEx pin voltage
Peak motor drive output current, t < 1 μS
Continuous motor drive output current⁽³⁾
Continuous total power dissipation
Operating virtual junction temperature range
Operating ambient temperature range
Storage temperature range
VALUE
UNIT
–0.3 to 47
V
–0.5 to 7
V
–0.3 to 4
V
–0.3 to 0.8
V
Internally limited
A
1.6
A
See Dissipation Ratings table
–40 to 150
°C
–40 to 85
°C
–60 to 150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
DISSIPATION RATINGS (PRELIMINARY)
BOARD
Low-K ⁽¹⁾
Low-K ⁽²⁾
High-K ⁽³⁾
High-K ⁽⁴⁾
PACKAGE
PWP
R_θJA
67.5°C/W
39.5°C/W
33.5°C/W
28°C/W
DERATING FACTOR
ABOVE T_A = 25°C
14.8 mW/°C
25.3 mW/°C
29.8 mW/°C
35.7 mW/°C
T_A < 25°C
1.85 W
3.16 W
3.73 W
4.46 W
T_A = 70°C
1.18 W
2.02 W
2.38 W
2.85 W
T_A = 85°C
0.96 W
1.64 W
1.94 W
2.32 W
(1) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.
(2) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm² 2-oz copper on back
side.
(3) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and
solid 1-oz internal ground plane.
(4) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm² 1-oz copper on back
side and solid 1-oz internal ground plane.
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