DLP9000_16 Datasheet, PDF (4/56 Pages) Texas Instruments – Family of 0.9 WQXGA Type A DMDs

DLP9000
DLPS036A – SEPTEMBER 2014 – REVISED OCTOBER 2015
www.ti.com
PIN ⁽¹⁾
NAME
DATA BUS A
D_AN(0)
D_AN(1)
D_AN(2)
D_AN(3)
D_AN(4)
D_AN(5)
D_AN(6)
D_AN(7)
D_AN(8)
D_AN(9)
D_AN(10)
D_AN(11)
D_AN(12)
D_AN(13)
D_AN(14)
D_AN(15)
D_AP(0)
D_AP(1)
D_AP(2)
D_AP(3)
D_AP(4)
D_AP(5)
D_AP(6)
D_AP(7)
D_AP(8)
D_AP(9)
D_AP(10)
D_AP(11)
D_AP(12)
D_AP(13)
D_AP(14)
D_AP(15)
DATA BUS B
D_BN(0)
D_BN(1)
D_BN(2)
D_BN(3)
D_BN(4)
D_BN(5)
D_BN(6)
D_BN(7)
NO.
H10
G3
G9
F4
F10
E3
E9
D2
J5
C9
F14
B8
G15
B14
H16
D16
H8
G5
G11
F2
F8
E5
E11
D4
J3
C11
F16
B10
H14
B16
G17
D14
AD8
AE3
AF8
AF2
AG5
AH8
AG9
AH2
TYPE
(I/O/P)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
SIGNAL
Pin Functions
DATA
RATE ⁽²⁾
INTERNAL
TERM ⁽³⁾
DESCRIPTION
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
TRACE
(mils) ⁽⁴⁾
737
737
737
738
739
739
737
737
739
736
743
737
739
740
737
737
737
738
737
736
739
738
737
737
739
737
741
737
739
739
737
737
739
737
736
739
737
737
737
739
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
(2) DDR = Double Data Rate.
SDR = Single Data Rate.
Refer to the Timing Requirements regarding specifications and relationships.
(3) Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions regarding differential termination
specification.
(4) Dielectric Constant for the DMD Type A ceramic package is approximately 9.6.
For the package trace lengths shown:
Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns.
Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
4
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