CD54AC74_14 Datasheet, PDF (4/15 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002
timing requirements over recommended operating free-air temperature range, V_CC = 1.5 V (unless
otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
trec
Recovery time, before CLK↑
PRE or CLR low
CLK
Data
PRE or CLR inactive
Data after CLK↑
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
9
50
56
44
0
34
–40°C to
85°C
MIN MAX
10
44
49
39
0
30
UNIT
MHz
ns
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
trec
Recovery time, before CLK↑
PRE or CLR low
CLK
Data
PRE or CLR inactive
Data after CLK↑
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
79
5.6
6.3
4.9
0
4.7
–40°C to
85°C
MIN MAX
90
4.9
5.5
4.3
0
4.1
UNIT
MHz
ns
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
trec
Recovery time, before CLK↑
PRE or CLR low
CLK
Data
PRE or CLR inactive
Data after CLK↑
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
110
4
4.5
3.5
0
2.7
–40°C to
85°C
MIN MAX
125
3.5
3.9
3.1
0
2.4
UNIT
MHz
ns
ns
ns
ns
ns
4
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